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1 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l 64m-bit single voltage 3v only uniform sector flash memory features general features ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program opera- tions configuration - 8,388,608 x 8 / 4,194,304 x 16 switchable (for mx29lv640m h/l) - 4,194,304 x 16 (for mx29lv641m h/l) sector structure - 64kb(32kw) x 128 sector protection/chip unprotect - provides sector group protect function to prevent program or erase operation in the protected sector group - provides chip unprotect function to allow code changes - provides temporary sector group unprotect function for code changes in previously protected sector groups secured silicon sector - provides a 128-word/256-byte area for code or data that can be permanently protected. - once this sector is protected, it is prohibited to pro- gram or erase within the sector again. latch-up protected to 250ma from -1v to vcc + 1v low vcc write inhibit is equal to or less than 1.5v compatible with jedec standard - pin-out and software compatible to single power sup- ply flash performance high performance - fast access time: 90ns - page read time: 25ns - sector erase time: 0.5s (typ.) - 4 word/8 byte page read buffer - 16 word/ 32 byte write buffer: reduces programming time for multiple-word/byte updates low power consumption - active read current: 18ma(typ.) - active write current: 20ma(typ.) - standby current: 20ua(typ.) minimum 100,000 erase/program cycle 20-years data retention software features support common flash interface (cfi) - flash device parameters stored on the device and provide the host system to access. program suspend/program resume - suspend program operation to read other sectors erase suspend/ erase resume - suspends sector erase operation to read data/pro- gram other sectors status reply - data# polling & toggle bits provide detection of pro- gram and erase operation completion hardware features ready/busy (ry/by#) output (for mx29lv640m h/l only) - provides a hardware method of detecting program and erase operation completion hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode wp#/acc input - write protect (wp#) function allows protection high- est or lowest sector, regardless of sector protection settings - acc (high voltage) accelerates programming time for higher throughput during system package 48-pin tsop (for mx29lv641m h/l) 56-pin tsop (for mx29lv640m h/l) general description the mx29lv64xm h/l is a 64-mega bit flash memory organized as 8m bytes of 8 bits or 4m words of 16 bits (for mx29lv640m h/l), or 4m words of 16bits (for mx29lv641m h/l). mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the mx29lv64xm h/l is pack- aged in 48-pin tsop and 56-pin tsop. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx29lv64xm h/l offers access time as fast as 90ns, allowing operation of high-speed micropro- cessors without wait states. to eliminate bus conten- tion, the mx29lv64xm h/l has separate chip enable
2 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l (ce#) and output enable (oe#) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx29lv64xm h/l uses a command register to manage this functionality. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29lv64xm h/l uses a 2.7v to 3.6v vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamperes on address and data pin from -1v to vcc + 1v. automatic programming the mx29lv64xm h/l is byte/word/page programmable using the automatic programming algorithm. the auto- matic programming algorithm makes the external sys- tem do not need to have time out sequence nor to verify the data programmed. automatic programming algorithm mxic's automatic programming algorithm require the user to only write program set-up commands (including 2 un- lock write cycle and a0h) and a program command (pro- gram data and address). the device automatically times the programming pulse width, provides the program veri- fication, and counts the number of sequences. a status bit similar to data# polling and a status bit toggling be- tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. automatic chip erase the entire chip is bulk erased using 50 ms erase pulses according to mxic's automatic chip erase algorithm. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and veri- fication of electrical erase are controlled internally within the device. automatic sector erase the mx29lv64xm h/l is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the tim- ing and verification of electrical erase are controlled inter- nally within the device. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we# . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the mx29lv64xm h/l electrically erases all bits simultaneously using fowler- nordheim tunneling. the bytes are programmed by us- ing the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
3 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l pin configuration 48 tsop for mx29lv641m h/l 56 tsop for mx29lv640m h/l a15 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 vi/o vss q15 q7 q14 q6 q13 q5 q12 q4 v cc q11 q3 q10 q2 q9 q1 q8 q0 oe# vss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx29lv641m h/l (normal type) nc nc a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc nc a16 byte# vss q15/a-1 q7 q14 q6 q13 q5 q12 q4 v cc q11 q3 q10 q2 q9 q1 q8 q0 oe# vss ce# a0 nc vio 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 mx29lv640m h/l (normal type)
4 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l symbol pin name a0~a21 address input q0~q14 data inputs/outputs q15/a-1 q15(word mode)/lsb addr(byte mode) ce# chip enable input we# write enable input oe# output enable input reset# hardware reset pin, active low wp#/acc hardware write protect/programming acceleration input ry/by# read/busy output byte# selects 8 bit or 16 bit mode vcc +3.0v single power supply vi/o output buffer power gnd device ground nc pin not connected internally pin description logic symbol 16 or 8 q0-q15 (a-1) ry/by# a0-a21 ce# oe# we# reset# wp#/acc byte# vi/o 22
5 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a0-a21 ce# oe# we# wp# byte# reset#
6 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l sector sector address sector size (x8) (x16) a21-a12 (kbytes/kwords) address range address range sa0 0000000xxx 64/32 000000h-00ffffh 000000h-07fffh sa1 0000001xxx 64/32 010000h-01ffffh 008000h-0ffffh sa2 0000010xxx 64/32 020000h-02ffffh 010000h-17fffh sa3 0000011xxx 64/32 030000h-03ffffh 018000h-01ffffh sa4 0000100xxx 64/32 040000h-04ffffh 020000h-027fffh sa5 0000101xxx 64/32 050000h-05ffffh 028000h-02ffffh sa6 0000110xxx 64/32 060000h-06ffffh 030000h-037fffh sa7 0000111xxx 64/32 070000h-07ffffh 038000h-03ffffh sa8 0001000xxx 64/32 080000h-08ffffh 040000h-047fffh sa9 0001001xxx 64/32 090000h-09ffffh 048000h-04ffffh sa10 0001010xxx 64/32 0a0000h-0affffh 050000h-057fffh sa11 0001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh sa12 0001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh sa13 0001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh sa14 0001110xxx 64/32 0e0000h-0effffh 070000h-077fffh sa15 0001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh sa16 0010000xxx 64/32 100000h-10ffffh 080000h-087fffh sa17 0010001xxx 64/32 110000h-11ffffh 088000h-08ffffh sa18 0010010xxx 64/32 120000h-12ffffh 090000h-097fffh sa19 0010011xxx 64/32 130000h-13ffffh 098000h-09ffffh sa20 0010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh sa21 0010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh sa22 0010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh sa23 0010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh sa24 0011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh sa25 0011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh sa26 0011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh sa27 0011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh sa28 0011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh sa29 0011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh sa30 0011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh sa31 0011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh sa32 0100000xxx 64/32 200000h-20ffffh 100000h-107fffh sa33 0100001xxx 64/32 210000h-21ffffh 108000h-10ffffh sa34 0100010xxx 64/32 220000h-22ffffh 110000h-117fffh sa35 0100011xxx 64/32 230000h-23ffffh 118000h-11ffffh sa36 0100100xxx 64/32 240000h-24ffffh 120000h-127fffh sa37 0100101xxx 64/32 250000h-25ffffh 128000h-12ffffh sa38 0100110xxx 64/32 260000h-26ffffh 130000h-137fffh sa39 0100111xxx 64/32 270000h-27ffffh 138000h-13ffffh mx29lv64xm h/l sector address table
7 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l sector sector address sector size (x8) (x16) a21-a12 (kbytes/kwords) address range address range sa40 0101000xxx 64/32 280000h-28ffffh 140000h-147fffh sa41 0101001xxx 64/32 290000h-29ffffh 148000h-14ffffh sa42 0101010xxx 64/32 2a0000h-2affffh 150000h-157fffh sa43 0101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh sa44 0101100xxx 64/32 2c0000h-2cffffh 160000h-147fffh sa45 0101101xxx 64/32 2d0000h-2dffffh 168000h-14ffffh sa46 0101110xxx 64/32 2e0000h-2effffh 170000h-177fffh sa47 0101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh sa48 0110000xxx 64/32 300000h-30ffffh 180000h-187fffh sa49 0110001xxx 64/32 310000h-31ffffh 188000h-18ffffh sa50 0110010xxx 64/32 320000h-32ffffh 190000h-197fffh sa51 0110011xxx 64/32 330000h-33ffffh 198000h-19ffffh sa52 0110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh sa53 0110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh sa54 0110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh sa55 0110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh sa56 0111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh sa57 0111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh sa58 0111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh sa59 0111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh sa60 0111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh sa61 0111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh sa62 0111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh sa63 0111111xxx 64/32 3f0000h-3fffffh 1f8000h-1fffffh sa64 1000000xxx 64/32 400000h-40ffffh 200000h-207fffh sa65 1000001xxx 64/32 410000h-41ffffh 208000h-20ffffh sa66 1000010xxx 64/32 420000h-42ffffh 210000h-217fffh sa67 1000011xxx 64/32 430000h-43ffffh 218000h-21ffffh sa68 1000100xxx 64/32 440000h-44ffffh 220000h-227fffh sa69 1000101xxx 64/32 450000h-45ffffh 228000h-22ffffh sa70 1000110xxx 64/32 460000h-46ffffh 230000h-237fffh sa71 1000111xxx 64/32 470000h-47ffffh 238000h-23ffffh sa72 1001000xxx 64/32 480000h-48ffffh 240000h-247fffh sa73 1001001xxx 64/32 490000h-49ffffh 248000h-24ffffh sa74 1001010xxx 64/32 4a0000h-4affffh 250000h-257fffh sa75 1001011xxx 64/32 4b0000h-4bffffh 258000h-25ffffh sa76 1001100xxx 64/32 4c0000h-4cffffh 260000h-247fffh sa77 1001101xxx 64/32 4d0000h-4dffffh 268000h-24ffffh sa78 1001110xxx 64/32 4e0000h-4effffh 270000h-277fffh sa79 1001111xxx 64/32 4f0000h-4fffffh 278000h-27ffffh
8 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l sector sector address sector size (x8) (x16) a21-a12 (kbytes/kwords) address range address range sa80 1010000xxx 64/32 500000h-50ffffh 280000h-287fffh sa81 1010001xxx 64/32 510000h-51ffffh 288000h-28ffffh sa82 1010010xxx 64/32 520000h-52ffffh 290000h-297fffh sa83 1010011xxx 64/32 530000h-53ffffh 298000h-29ffffh sa84 1010100xxx 64/32 540000h-54ffffh 2a0000h-2a7fffh sa85 1010101xxx 64/32 550000h-55ffffh 2a8000h-2affffh sa86 1010110xxx 64/32 560000h-56ffffh 2b0000h-2b7fffh sa87 1010111xxx 64/32 570000h-57ffffh 2b8000h-2bffffh sa88 1011000xxx 64/32 580000h-58ffffh 2c0000h-2c7fffh sa89 1011001xxx 64/32 590000h-59ffffh 2c8000h-2cffffh sa90 1011010xxx 64/32 5a0000h-5affffh 2d0000h-2d7fffh sa91 1011011xxx 64/32 5b0000h-5bffffh 2d8000h-2dffffh sa92 1011100xxx 64/32 5c0000h-5cffffh 2e0000h-2e7fffh sa93 1011101xxx 64/32 5d0000h-5dffffh 2e8000h-2effffh sa94 1011110xxx 64/32 5e0000h-5effffh 2f0000h-2f7fffh sa95 1011111xxx 64/32 5f0000h-5fffffh 2f8000h-2fffffh sa96 1100000xxx 64/32 600000h-60ffffh 300000h-307fffh sa97 1100001xxx 64/32 610000h-61ffffh 308000h-30ffffh sa98 1100010xxx 64/32 620000h-62ffffh 310000h-317fffh sa99 1100011xxx 64/32 630000h-63ffffh 318000h-31ffffh sa100 1100100xxx 64/32 640000h-64ffffh 320000h-327fffh sa101 1100101xxx 64/32 650000h-65ffffh 328000h-32ffffh sa102 1100110xxx 64/32 660000h-66ffffh 330000h-337fffh sa103 1100111xxx 64/32 670000h-67ffffh 338000h-33ffffh sa104 1101000xxx 64/32 680000h-68ffffh 340000h-347fffh sa105 1101001xxx 64/32 690000h-69ffffh 348000h-34ffffh sa106 1101010xxx 64/32 6a0000h-6affffh 350000h-357fffh sa107 1101011xxx 64/32 6b0000h-6bffffh 358000h-35ffffh sa108 1101100xxx 64/32 6c0000h-6cffffh 360000h-347fffh sa109 1101101xxx 64/32 6d0000h-6dffffh 368000h-34ffffh sa110 1101110xxx 64/32 6e0000h-6effffh 370000h-377fffh sa111 1101111xxx 64/32 6f0000h-6fffffh 378000h-37ffffh sa112 1110000xxx 64/32 700000h-70ffffh 380000h-387fffh sa113 1110001xxx 64/32 710000h-71ffffh 388000h-38ffffh sa114 1110010xxx 64/32 720000h-72ffffh 390000h-397fffh sa115 1110011xxx 64/32 730000h-73ffffh 398000h-39ffffh sa116 1110100xxx 64/32 740000h-74ffffh 3a0000h-3a7fffh sa117 1110101xxx 64/32 750000h-75ffffh 3a8000h-3affffh sa118 1110110xxx 64/32 760000h-76ffffh 3b0000h-3b7fffh sa119 1110111xxx 64/32 770000h-77ffffh 3b8000h-3bffffh
9 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l note:the address range is a21:a-1 in byte mode (byte#=vil) or a20:a0 in word mode (byte#=vih) sector sector address sector size (x8) (x16) a21-a12 (kbytes/kwords) address range address range sa120 1111000xxx 64/32 780000h-78ffffh 3c0000h-3c7fffh sa121 1111001xxx 64/32 790000h-79ffffh 3c8000h-3cffffh sa122 1111010xxx 64/32 7a0000h-7affffh 3d0000h-3d7fffh sa123 1111011xxx 64/32 7b0000h-7bffffh 3d8000h-3dffffh sa124 1111100xxx 64/32 7c0000h-7cffffh 3e0000h-3e7fffh sa125 1111101xxx 64/32 7d0000h-7dffffh 3e8000h-3effffh sa126 1111110xxx 64/32 7e0000h-7effffh 3f0000h-3f7fffh sa127 1111111xxx 64/32 7f0000h-7fffffh 3f8000h-3fffffh
10 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l mx29lv640m h/l sector group protection ad- dress table sector group a21-a15 sa0 0000000 sa1 0000001 sa2 0000010 sa3 0000011 sa4-sa7 00001xx sa8-sa11 00010xx sa12-sa15 00011xx sa16-sa19 00100xx sa20-sa23 00101xx sa24-sa27 00110xx sa28-sa31 00111xx sa32-sa35 01000xx sa36-sa39 01001xx sa40-sa43 01010xx sa44-sa47 01011xx sa48-sa51 01100xx sa52-sa55 01101xx sa56-sa59 01110xx sa60-sa63 01111xx sa64-sa67 10000xx sa68-sa71 10001xx sa72-sa75 10010xx sa76-sa79 10011xx sa80-sa83 10100xx sa84-sa87 10101xx sa88-sa91 10110xx sa92-sa95 10111xx sa96-sa99 11000xx sa100-sa103 11001xx sa104-sa107 11010xx sa108-sa111 11011xx sa112-sa115 11100xx sa116-sa119 11101xx sa120-sa123 11110xx sa124 1111100 sa125 1111101 sa126 1111110 sa127 1111111 mx29lv641m h/l sector group protection ad- dress table sector group a21-a15 sa0-sa3 00000 sa4-sa7 00001 sa8-sa11 00010 sa12-sa15 00011 sa16-sa19 00100 sa20-sa23 00101 sa24-sa27 00110 sa28-sa31 00111 sa32-sa35 01000 sa36-sa39 01001 sa40-sa43 01010 sa44-sa47 01011 sa48-sa51 01100 sa52-sa55 01101 sa56-sa59 01110 sa60-sa63 01111 sa64-sa67 10000 sa68-sa71 10001 sa72-sa75 10010 sa76-sa79 10011 sa80-sa83 10100 sa84-sa87 10101 sa88-sa91 10110 sa92-sa95 10111 sa96-sa99 11000 sa100-sa103 11001 sa104-sa107 11010 sa108-sa111 11011 sa112-sa115 11100 sa116-sa119 11101 sa120-sa123 11110 sa124-sa127 11111
11 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l q8~q15 operation ce# oe# we# re- wp# acc address q0~q7 word byte set# mode mode read l l h h x x a in d out d out q8-q14= high z q15=a-1 write (program/erase) l h l h (note 3) x a in (note 4) (note 4 q8-q14= high z q15=a-1 accelerated program l h l h (note 3) v hh a in (note 4) (note 4) q8-q14= high z q15=a-1 standby vcc x x vcc x h x high-z high-z high-z 0.3v 0.3v output disable l h h h x x x high-z high-z high-z reset x x x l x x x high-z high-z high-z sector group protect l h l v id h x sector addresses, (note 4) x x (note 2) a6=l,a3=l, a2=l, a1=h,a0=l chip unprotect l h l v id h x sector addresses, (note 4) x x (note 2) a6=h, a3=l, a2=l, a1=h, a0=l temporary sector x x x v id hx a in (note 4) (note 4) high-z group unprotect legend: l=logic low=v il , h=logic high=v ih , v id =12.0 0.5v, v hh =12.0 0.5v, x=don't care, a in =address in, d in =data in, d out =data out notes: 1. address are a21:a0 in word mode; a21:a-1 in byte mode. sector addresses are a21:a15 in both modes. 2. the sector group protect and chip unprotect functions may also be implemented via programming equipment. see the "sector group protection and chip unprotect" section. 3. if wp#=vil, the first sectors remain protected. if wp#=vih, the highest or lowest sector protection depends on whether they were last protected or unprotect using the method described in "sector/ sector block protection and unprotect". 4. d in or d out as required by command sequence, data# polling or sector protect algorithm (see figure 15). table 1. bus operation (1)
12 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l table 2. autoselect codes (high voltage method) a21 a14 a8 a5 a3 q8 to q15 q7 to q0 description ce# oe# we# to to a9 to a6 to to a1 a0 word byte a15 a10 a7 a4 a2 mode mode manufacturer id l l h x x vid x l x l l l 00 x c2h cycle 1 l l h 22 x 7eh cycle 2 l l h x x vid x l x h h l 22 x 0ch cycle 3 h h h 22 x 01h cycle 1 l l h 22 - 7eh cycle 2 l l h x x vid x l x h h l 22 - 13h cycle 3 h h h 22 - 01h sector group 01h (protected), protection l l h sa x vid x l x l h l x x verification 00h (unprotected) secured silicon 98h sector indicator (factory locked), bit (q7), wp# l l h x x vid x l x l h h x x protects highest 18h address sector (not factory locked) secured silicon 88h sector indicator (factory locked), bit (q7), wp# l l h x x vid x l x l h h x x protects lowest 08h address sector (not factory locked) legend: l = logic low = vil, h = logic high = vih, sa = sector address, x = don't care. 29lv640mh/l 29lv641mh/l
13 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to vil. ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should re- main at vih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory con- tent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the de- vice data outputs. the device remains enabled for read access until the command register contents are altered. page mode read the mx29lv64xm h/l offers "fast page mode read" func- tion. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words/8 bytes. the appropriate page is se- lected by the higher address bits a0~a1(word mode)/a- 1~a1(byte mode) this is an asynchronous operation; the microprocessor supplies the specific word location. the system performance could be enhanced by initiating 1 normal read and 3 fast page read (for word mode a0- a1) or 7 fast page read (for byte mode a-1~a1). when ce# is deasserted and reasserted for a subsequent ac- cess, the access time is tacc or tce. fast page mode accesses are obtained by keeping the "read-page ad- dresses" constant and changing the "intra-read page" addresses. writing commands/command se- quences to program data to the device or erase sectors of memory, the system must drive we# and ce# to vil, and oe# to vih. an erase operation can erase one sector, multiple sec- tors, or the entire device. table indicates the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. the "writing specific address and data commands or sequences into the command register initiates device operations. table 1 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the automatic select command sequence, the device enters the automatic select mode. the system can then read automatic select codes from the internal register (which is separate from the memory array) on q7-q0. standard read cycle timings apply in this mode. refer to the automatic select mode and au- tomatic select command sequence section for more information. icc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. write buffer write buffer programming allows the system to write a maximum of 16 words/32 bytes in one programming op- eration. this results in faster effective programming time than the standard programming algorithms. see "write buffer" for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the acc pin. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts vhh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing vhh from the acc pin must not be at vhh for operations other than accel- erated programming, or device damage may result.
14 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l standby mode when using both pins of ce# and reset#, the device enter cmos standby with both pins held at vcc 0.3v. if ce# and reset# are held at vih, but not within the range of vcc 0.3v, the device will still be in the standby mode, but the standby current will be larger. during auto algorithm operation, vcc active current (icc2) is required even ce# = "h" until the operation is completed. the device can be read with standard access time (tce) from either of these standby modes, before it is ready to read data. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when address remain stable for tacc+30ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access tim- ings provide new data when addresses are changed. while in sleep mode, output data is latched and always avail- able to the system. icc4 in the dc characteristics table represents the automatic sleep mode current specifica- tion. output disable with the oe# input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. reset# operation the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity current is reduced for the duration of the reset# pulse. when reset# is held at vss 0.3v, the device draws cmos standby current (icc4). if reset# is held at vil but not within vss 0.3v, the standby current will be greater. the reset# pin may be tied to system reset circuitry. a system reset would that also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is completed within a time of tready (not during embedded algorithms). the system can read data trh after the reset# pin returns to vih. refer to the ac characteristics tables for reset# parameters and to figure 3 for the timing diagram. sector group protect operation the mx29lv64xm h/l features hardware sector group protection. this feature will disable both program and erase operations for these sector group protected. in this device, a sector group consists of four adjacent sec- tors which are protected or unprotected at the same time. to activate this mode, the programming equipment must force vid on address pin a9 and control pin oe#, (sug- gest vid = 12v) a6 = vil and ce# = vil. (see table 2) programming of the protection circuitry begins on the falling edge of the we# pulse and is terminated on the rising edge. please refer to sector group protect algo- rithm and waveform. mx29lv64xm h/l also provides another method. which requires vid on the reset# only. this method can be implemented either in-system or via programming equip- ment. this method uses standard microprocessor bus cycle timing. to verify programming of the protection circuitry, the pro- gramming equipment must force vid on address pin a9 ( with ce# and oe# at vil and we# at vih). when a1=1, it will produce a logical "1" code at device output q0 for a protected sector. otherwise the device will pro- duce 00h for the unprotected sector. in this mode, the addresses, except for a1, are don't care. address loca- tions with a1 = vil are reserved to read manufacturer and device codes. (read silicon id)
15 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l it is also possible to determine if the group is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector. chip unprotect operation the mx29lv64xm h/l also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. to activate this mode, the programming equipment must force vid on control pin oe# and address pin a9. the ce# pins must be set at vil. pins a6 must be set to vih. (see table 2) refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. the unprotect mechanism begins on the falling edge of the we# pulse and is terminated on the rising edge. mx29lv64xm h/l also provides another method. which requires vid on the reset# only. this method can be implemented either in-system or via programming equip- ment. this method uses standard microprocessor bus cycle timing. it is also possible to determine if the chip is unprotect in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs (q0-q7) for an unprotect sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. write protect (wp#) the write protect function provides a hardware method to protect sector without using v id . if the system asserts vil on the wp# pin, the device disables program and erase functions in the first (mx29lv64xmh) or last (mx29lv64xml) sector inde- pendently of whether those sectors were protected or unprotect using the method described in sector/sector group protection and chip unprotect". if the system asserts vih on the wp# pin, the device reverts to whether the first (mx29lv64xmh) or last (mx29lv64xml) sector were last set to be protected or unprotect. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotect using the method described in "sector/sector group protection and chip unprotect". note that the wp# pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. temporary sector group unprotect operation this feature allows temporary unprotect of previously protected sector to change data in-system. the tempo- rary sector unprotect mode is activated by setting the reset# pin to vid(11.5v-12.5v). during this mode, for- merly protected sectors can be programmed or erased as unprotect sector. once vid is remove from the re- set# pin, all the previously protected sectors are pro- tected again. silicon id read operation flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. mx29lv64xm h/l provides hardware method to access the silicon id read operation. which method requires vid on a9 pin, vil on ce#, oe#, a6, and a1 pins. which apply vil on a0 pin, the device will output mxic's manu- facture code of which apply vih on a0 pin, the device will output mx29lv64xm h/l device code. verify sector group protect status operation mx29lv64xm h/l provides hardware method for sector group protect status verify. which method requires vid on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6, and a0 pins, and sector address on a16 to a21 pins. which the identified sector is protected, the device will output 01h. which the identified sector is not protect, the device will output 00h.
16 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l data protection the mx29lv64xm h/l is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically re- sets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down tran- sition or system noise. secured silicon sector the mx29lv64xm h/l features a otp memory region where the system may access through a command se- quence to create a permanent part identification as so called electronic serial number (esn) in the device. once this region is programmed, any further modifica- tion on the region is impossible. the secured silicon sec- tor is a 128 words in length, and uses a secured silicon sector indicator bit (q7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevent duplication of a fac- tory locked part. this ensures the security of the esn once the product is shipped to the field. the mx29lv64xm h/l offers the device with secured silicon sector either factory locked or customer lock- able. the factory-locked version is always protected when shipped from the factory , and has the secured silicon sector indicator bit permanently set to a "1". the cus- tomer-lockable version is shipped with the secured sili- con sector unprotected, allowing customers to utilize that sector in any form they prefer. the customer-lockable version has the secured sector indicator bit permanently set to a "0". therefore, the secured silicon sector indi- cator bit prevents customer, lockable device from being used to replace devices that are factory locked. the system access the secured silicon sector through a command sequence (refer to "enter secured silicon/ exit secured silicon sector command sequence). after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the address normally occupied by the first sector sa0. once entry the secured silicon sector the operation of boot sectors is disabled but the operation of main sectors is as normally. this mode of operation continues until the system issues the exit secured sili- con sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending command to sector sa0. secured silicon esn factory customer sector address locked lockable range 000000h-000007h esn determined by 000008h-00007fh unavailable customer factory locked:secured silicon sector programmed and protected at the factory in device with an esn, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. a factory locked device has an 8-word random esn at address 000000h-000007h. customer lockable:secured silicon sector not programmed or protected at the factory as an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word secured silicon sector. programming and protecting the secured silicon sector must be used with caution since, once protected, there is no procedure available for unprotected the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be protected using one of the following procedures: write the three-cycle enter secured silicon sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 15, except that reset# may be at either vih or vid. this allows in- system protection of the secured silicon sector without raising any device pin to a high voltage. note that method is only applicable to the secured silicon sector.
17 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l write the three-cycle enter secured silicon sector region command sequence, and then alternate method of sector protection described in the :sector group protection and unprotect" section. once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array. low vcc write inhibit when vcc is less than vlko the device does not ac- cept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than vlko. the system must provide the proper signals to the control pins to prevent unintentional write when vcc is greater than vlko. write pulse "glitch" protection noise pulses of less than 5ns (typical) on ce# or we# will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe# = vil, ce# = vih or we# = vih. to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. power-up sequence the mx29lv64xm h/l powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. power-up write inhibit if we#=ce#=vil and oe#=vih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. power supply de coupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd.
18 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l table 3. mx29lv64xm h/l command definitions first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycles addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 automatic select (note 7) manufacturer id word 4 555 aa 2aa 55 555 90 x00 c2h byte 4 aaa aa 555 55 aaa 90 x00 c2h device id word 4 555 aa 2aa 55 555 90 x01 id1 x0e id2 x0f id3 (note 8) byte 4 aaa aa 555 55 aaa 90 x02 id1 x1c id2 x1e id3 secured sector fact- word 4 555 aa 2aa 55 555 90 x03 see ory protect (note 9) byte 4 aaa aa 555 55 aaa 90 x06 note 9 sector group protect word 4 555 aa 2aa 55 555 90 (sa)x02 xx00/ verify (note 10) byte 4 aaa aa 555 55 aaa 90 (sa)x04 xx01 enter secured silicon word 3 555 aa 2aa 55 555 88 sector byte 3 aaa aa 555 55 aaa 88 exit secured silicon word 4 555 aa 2aa 55 555 90 xxx 00 sector byte 4 aaa aa 555 55 aaa 90 xxx 00 program word 4 555 aa 2aa 55 555 a0 pa pd byte 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 11) word 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd byte 6 aaa aa 555 55 sa 25 sa bc pa pd wbl pd program buffer to flash word 1 sa 29 byte 1 sa 29 write to buffer abort word 3 555 aa 2aa 55 555 f0 reset (note 12) byte 3 aaa aa 555 55 aaa f0 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend (note 13) 1 xxx b0 program/erase resume (note 14) 1 xxx 30 cfi query (note 15) word 1 55 98 byte 1 aa 98 software command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 3 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device (when applicable). all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data are latched on rising edge of we# or ce#, whichever happens first.
19 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l notes: 1. see table 1 for descriptions of bus operations. 2. all values are in hexadecimal. 3. except when reading array or automatic select data, all bus cycles are write operation. 4. address bits are don't care for unlock and command cycles, except when pa or sa is required. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode when the device is in the automatic select mode or if q5 goes high. 7. the fourth cycle of the automatic select command sequence is a read cycle. 8. the device id must be read in three cycles. the data is 01h for top boot and 00h for bottom boot. 9. if wp# protects the highest address sectors, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the lowest address sectors, the data is 88h for factory locked and 08h for not factor locked. 10. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 21(word mode) / 37(byte mode). 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. the system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. 15. command is valid when device is ready to read array data or when device is in automatic select mode. legend: x=don't care ra=address of the memory location to be read. rd=data read from location ra during read operation. pa=address of the memory location to be programmed. addresses are latched on the falling edge of the we# or ce# pulse, whichever happen later. ddi=data of device identifier c2h for manufacture code pd=data to be programmed at location pa. data is latched on the rising edge of we# or ce# pulse. sa=address of the sector to be erase or verified (in autoselect mode). address bits a21-a12 uniquely select any sector. wbl=write buffer location. address must be within the same write buffer page as pa. wc=word count. number of write buffer locations to load minus 1. bc=byte count. number of write buffer locations to load minus 1.
20 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l reading array data the device is automatically set to reading array data after device power-up. no commands are required to re- trieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. af- ter completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high, or while in the automatic select mode. see the "reset com- mand" section, next. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase sus- pend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an silicon id read command se- quence. once in the silicon id read mode, the reset command must be written to return to reading array data (also applies to silicon id read during erase sus- pend). if q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). silicon id read command sequence the silicon id read command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is pro- tected. table 2 shows the address and data requirements. this method is an alternative to that shown in table 1, which is intended for prom programmers and requires vid on address bit a9. the silicon id read command sequence is initiated by writing two unlock cycles, followed by the silicon id read command. the device then enters the sili- con id read mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. refer to table for valid sector addresses. the system must write the reset command to exit the automatic select mode and return to reading array data. byte/word program command se- quence the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the em- bedded program algorithm. the system is not required to provide further controls or timings. the device auto- matically generates the program pulses and verifies the programmed cell margin. table 3 shows the address and data requirements for the byte program command se- quence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6, or ry/ by#. see "write operation status" for information on these status bits. any commands written to the device during the embed- ded program algorithm are ignored. note that a hard-
21 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l ware reset immediately terminates the programming op- eration. the byte/word program command sequence should be reinitiated once the device has reset to read- ing array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a "0" back to a "1". attempting to do so may halt the op- eration and set q5 to "1", or cause the data# polling algorithm to indicate the operation was successful. how- ever, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1". write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming op- eration. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be pro- grammed. for example, if the system will program 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the num- ber of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max -4. all subsequent address/data pairs must fall within the selected-write-buffer-page. the sys- tem then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer pages. this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load program- ming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host sys- tem must therefore account for loading a write-buffer lo- cation more than once. the counter decrements for each data load operation, not for each unique write-buffer-ad- dress location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitor- ing the last address location loaded into the write buffer. q7, q6, q5, and q1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer program- ming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load command. write an address/data pair to a different write-buffer- page than the one selected by the starting address during the write buffer data loading stage of the op- eration. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by q1 = 1, q7 = data# (for the last address location loaded), q6 = toggle, and q5=0. a write-to-buffer-abort reset command sequence must be written to reset the device for the next opera- tion. note that the full 3-cycle write-to-buffer-abort re- set command sequence is required when using write- buffer-programming features in unlock bypass mode. program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer
22 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l programming operation so that data can be read from any non-suspended sector. when the program suspend com- mand is written during a programming process, the de- vice halts the program operation within 15us maximum (5 us typical) and updates the status bits. addresses are not required when writing the program suspend com- mand. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect com- mand sequence for more information. after the program resume command is written, the de- vice reverts to programming. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. see write operation status for more information. setup automatic chip/sector erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h, or the sector erase command 30h. the mx29lv64xm h/l contains a silicon-id-read op- eration to supplement traditional prom programming methodology. the operation is initiated by writing the read silicon id command sequence into the command regis- ter. following the command write, a read cycle with a1=vil,a0=vil retrieves the manufacturer code. a read cycle with a1=vil, a0=vih returns the device code. automatic chip/sector erase com- mand the device does not require the system to preprogram prior to erase. the automatic erase algorithm automati- cally pre-program and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 3 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the automatic erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase op- eration by using q7, q6, q2, or ry/by#. see "write op- eration status" for information on these status bits. when the automatic erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 10 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in "ac characteristics" for parameters, and to figure 9 for tim- ing diagrams.
23 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l sector erase commands the automatic sector erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic set-up sector erase command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up com- mand 80h. two more "unlock" write cycles are then fol- lowed by the sector erase command 30h. the sector address is latched on the falling edge of we# or ce#, whichever happens later , while the command (data) is latched on the rising edge of we# or ce#, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we# or ce#, whichever happens later. each successive sector load cycle started by the falling edge of we# or ce#, whichever happens later must begin within 50us from the rising edge of the preceding we# or ce#, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time-out period resets the device to read mode. erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend com- mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after this command has been executed, the command register will initiate erase suspend mode. the state machine will return to read mode automatically after suspend is ready. at this time, state machine only allows the command register to re- spond to the erase resume, program data to, or read data from any sector not selected for erasure. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended blocks. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing.
24 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l table 4-1. cfi mode: identification data values (all values in these tables are in hexadecimal) description address h address h data h (x16) (x8) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 address for primary algorithm extended query table 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code (none) 17 2e 0000 18 30 0000 address for secondary algorithm extended query table (none) 19 32 0000 1a 34 0000 table 4-2. cfi mode: system interface data values description address h address h data h (x16) (x8) vcc supply, minimum (2.7v) 1b 36 0027 vcc supply, maximum (3.6v) 1c 38 0036 vpp supply, minimum (none) 1d 3a 0000 vpp supply, maximum (none) 1e 3c 0000 typical timeout for single word/byte write (2 n us) 1f 3e 0007 typical timeout for maximum size buffer write (2 n us) 20 40 0007 typical timeout for individual block erase (2 n ms) 21 42 000a typical timeout for full chip erase (2 n ms) 22 44 0000 maximum timeout for single word/byte write times (2 n x typ) 23 46 0001 maximum timeout for maximum size buffer write times (2 n x typ) 24 48 0005 maximum timeout for individual block erase times (2 n x typ) 25 4a 0004 maximum timeout for full chip erase times (not supported) 26 4c 0000 query command and common flash interface (cfi) mode mx29lv64xm h/l is capable of operating in the cfi mode. this mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. two commands are required in cfi mode. query command of cfi mode is placed first, then the reset command exits cfi mode. these are described in table 4. the single cycle query command is valid only when the device is in the read mode, including erase suspend, standby mode, and read id mode; however, it is ignored otherwise. the reset command exits from the cfi mode to the read mode, or erase suspend mode, or read id mode. the command is valid only when the device is in the cfi mode.
25 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l description address h address h data h (x16) (x8) device size (2 n bytes) 27 4e 0017 flash device interface code 28 50 000x 0002h = mx29lv640m h/l 29 52 0000 0001h = mx29lv641m h/l maximum number of bytes in multi-byte write (not supported) 2a 54 0005 2b 56 0000 number of erase block regions (01h=uniform device; 02h=boot device) 2c 58 0001 erase block region 1 information 2d 5a 007f [2e,2d] = # of blocks in region -1 2e 5c 0000 [30, 2f] = size in multiples of 256-bytes 2f 5e 0000 30 60 0001 31h 62 0000 erase block region 2 information (refer to cfi publication 100) 32h 64 0000 33h 66 0000 34h 68 0000 35h 6a 0000 erase block region 3 information (refer to cfi publication 100) 36h 6c 0000 37h 6e 0000 38h 70 0000 39h 72 0000 erase block region 4 information (refer to cfi publication 100) 3ah 74 0000 3bh 76 0000 3ch 78 0000 table 4-3. cfi mode: device geometry data values
26 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l description address h address h data h (x16) (x8) query-unique ascii string "pri" 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0033 address sensitive unlock (0=required, 1= not required) 45 8a 0000 erase suspend (2= to read and write) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 000x 0001h = mx29lv640m h/l 0004h = mx29lv641m h/l temporary sector unprotect (1=supported) 48 90 0001 sector protect/unprotect scheme 49 92 0004 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode type (0=not supported) 4b 96 0000 page mode type (1=4 word page) 4c 98 0001 acc (acceleration) supply minimum 4dh 9a 00b5 00h=not supported, d7-d4: volt, d3-d0:100mv acc (acceleration) supply maximum 4eh 9c 00c5 00h=not supported, d7-d4: volt, d3-d0:100mv top/bottom boot sector flag 4fh 9e 0004/ 02h=bottom boot device, 03h=top boot device 0005 04h=uniform sectors bottom wp# protect, 05h=uniform sectors top wp# protect program suspend 50h a0 0001 00h=not supported, 01h=supported table 4-4. cfi mode: primary vendor-specific extended query data values
27 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l table 5. write operation status write operation status the device provides several bits to determine the status of a write operation: q2, q3, q5, q6, q7, and ry/by#. table 5 and the following subsections describe the func- tions of these bits. q7, ry/by#, and q6 each offer a method for determining whether a program or erase op- eration is complete or in progress. these three bits are discussed first. status q7 q6 q5 q3 q2 q1 ry/by# byte/word program in auto program algorithm q7# to ggle 0 n/a no 0 0 toggle auto erase algorithm 0 to ggle 0 1 toggle n/a 0 erase suspend read 1 no 0 n/a to ggle n/a 1 erase (erase suspended sector) to ggle suspended erase suspend read data data data data data data 1 mode (non-erase suspended sector) erase suspend program q7# to ggle 0 n/a n/a n/a 0 program-suspended read invalid (not allowed) 1 program (program-suspended sector) suspend program-suspended read data 1 (non-program-suspended sector) write-to-buffer busy q7# toggle 0 n/a n/a 0 0 abort q7# toggle 0 n/a n/a 1 0 notes: 1. q5 switches to "1" when an word/byte program, erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on q5 for more information. 2. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. q1 switches to "1" when the device has aborted the write-to-buffer operation.
28 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l q7: data# polling the data# polling bit, q7, indicates to the host system whether an automatic algorithm is in progress or com- pleted, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming dur- ing erase suspend. when the automatic program algo- rithm is complete, the device outputs the datum pro- grammed to q7. the system must provide the program address to read valid status information on q7. if a pro- gram address falls within a protected sector, data# poll- ing on q7 is active for approximately 1 us, then the de- vice returns to reading array data. during the automatic erase algorithm, data# polling pro- duces a "0" on q7. when the automatic erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a "1" on q7. this is analo- gous to the complement/true datum output described for the automatic program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". the system must provide an address within any of the sectors se- lected for erasure to read valid status information on q7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on q7 is active for approximately 100 us, then the device returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects q7 has changed from the complement to true data, it can read valid data at q7-q0 on the following read cycles. this is because q7 may change asynchronously with q0-q6 while output enable (oe#) is asserted low. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# or ce#, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, q6 toggles for 100us and returns to reading array data. if not all se- lected sectors are protected, the automatic erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing (that is, the auto- matic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to de- termine which sectors are erasing or erase-suspended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2us after the program com- mand sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algo- rithm is complete. table 5 shows the outputs for toggle bit i on q6. q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# or ce#, whichever happens first pulse in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com-
29 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 5 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase opera- tion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the al- gorithm when it returns to determine the status of the operation. q5:program/erase timing q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data# polling and toggle bit are the only operating functions of the device under this con- dition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte/word pro- gramming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be re- used). the time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the au- tomatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. the q5 failure condition may appear if the system tries to program a to a "1" location that is previously pro- grammed to "0". only an erase operation can change a "0" back to a "1". under this condition, the device halts the operation, and when the operation has exceeded the timing limits, q5 produces a "1". q3:sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data# polling and toggle bit are valid after the initial sector erase com- mand sequence. if data# polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data# polling or
30 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l toggle bit. if q3 is low ("0"), the device will accept addi- tional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. if the time between additional erase commands from the system can be less than 50us, the system need not to monitor q3. q1: write-to-buffer abort q1 indicates whether a write-to-buffer operation was aborted. under these conditions q1 produces a "1". the system must issue the write-to-buffer-abort-reset com- mand sequence to return the device to reading array data. see write buffer section for more details. ry/by#:ready/busy output (for mx29lv640m h/l only) the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode.
31 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe#, and reset# (note 2) . . . . . . . . . . . ....-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. maxi- mum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may over- shoot to vcc +2.0 v for periods up to 20ns. 2. minimum dc input voltage on pins a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot vss to -2.0 v for peri- ods of up to 20 ns. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for peri- ods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40 c to +85 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
32 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = vil is 5.0ua. 2. maximum icc specifications are tested with vcc = vcc max. 3. the icc current listed is typically is less than 2 ma/mhz, with oe# at vih. typical specifications are for vcc = 3.0v. 4. icc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. not 100% tested. 7. a9=12.5v when ta=0 c to 85 c, a9=12v when when ta=-40 c to 0 c. dc characteristics ta=-40 c to 85 c, vcc=2.7v~3.6v para- meter description test conditions min. typ. max. unit i li input load current (note 1) vin = vss to vcc , 1.0 ua vcc = vcc max i lit a9 input leakage current vcc=vcc max; a9 = 12.5v 35 ua i lo output leakage current v out = vss to vcc , 1.0 ua vcc= vcc max icc1 vcc initial read current ce#= vil, 10 mhz 35 50 ma (notes 2,3) oe# = vih 5 mhz 18 25 ma 1 mhz 5 20 ma icc2 vcc intra-page read ce#= vil , 10 mhz 5 20 ma current (notes 2,3) oe# = vih 40 mhz 10 40 ma icc3 vcc active wr ite current ce#= vil , oe# = vih 50 60 ma (notes 2,4,6) icc4 vcc standby current ce#,reset#=vcc 0.3v 20 50 ua (note 2) wp#=vih icc5 vcc reset current reset#=vss 0.3v 20 50 ua (note 2) wp#=vih icc6 auto matic sleep mode vil = v ss 0.3 v, 20 50 ua (note 2,5) vih = vcc 0.3 v, wp#=vih vil input low voltage -0.5 0.8 v vih input high voltage 0.7xvcc vcc+0.5 v vhh voltage for acc program vcc = 2.7v ~ 3.6v 11.5 12.0 12.5 v acceleration vid voltage for autoselect and vcc = 3.0 v 10% 11.5 12.0 12.5 v temporary sector unprotect vol output low voltage iol= 4.0ma,vcc=vcc min 0.45 v voh1 output high voltage ioh=-2.0ma,vcc=vcc min 0.85vcc v voh2 ioh=-100ua,vcc=vcc min vcc-0.4 v vlko low vcc lock-out voltage 2.3 2.5 v (note 4)
33 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l switching test circuits waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state(high z) key to switching waveforms switching test waveforms test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, cl 30 pf (including jig capacitance) input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement 1.5 v reference levels output timing measurement 1.5 v reference levels device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm 3.3v 1.5v 1.5v measurement level 3.0v 0.0v output input
34 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l ac characteristics read-only operations ta=-40 c to 85 c, vcc=2.7v~3.6v parameter speed options std. description test setup 90 unit trc read cycle time (note 1) min 90 ns tacc address to output delay ce#, oe#=vil max 90 ns tce chip enable to output delay oe#=vil max 90 ns tpacc page access time max 25 ns toe output enable to output delay max 35 ns tdf chip enable to output high z (note 1) max 16 ns tdf output enable to output high z (note 1) max 16 ns toh output hold time from address, ce# min 0 ns or oe#, whichever occurs first read min 35 ns toeh output enable hold time to ggle and min 10 ns (note 1) data# polling notes: 1. not 100% tested. 2. see switching test circuits and test specifications table for test specifications.
35 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 1. read timing waveforms addresses ce# oe# tacc we# vih vil vih vil vih vil vih vil 0v vih vil voh vol high z high z data valid toe toeh tdf tce trh trh trc outputs reset# ry/by# toh add valid figure 2. page read timing waveforms same page a2-a21 (a-1), a0~a2 ce# oe# output tacc tpacc tpacc tpacc qa qb qc qd
36 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 3. reset# timing waveform ac characteristics parameter description test setup all speed options unit tready1 reset# pin low (during automatic algorithms) max 20 us to read or write (see note) tready2 reset# pin low (not during automatic algorithms) max 500 ns to read or write (see note) trp reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read (see note) min 50 ns trb ry/by# recovery time(to ce#, oe# go low) min 0 ns trpd reset# low to standby mode min 20 us note:not 100% tested trh trb tready1 trp trp tready2 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# reset#
37 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l ac characteristics erase and program operations ta=-40 c to 85 c, vcc=2.7v~3.6v parameter speed options std. description 90 unit twc write cycle time (note 1) min 90 ns tas address setup time min 0 ns taso address setup time to oe# low during toggle bit polling min 15 ns tah address hold time min 45 ns taht address hold time from ce# or oe# high during toggle min 0 ns bit polling tds data setup time min 35 ns tdh data hold time min 0 ns tceph ce# high during toggle bit polling min 20 ns toeph output enable high during toggle bit polling min 20 ns tghwl read recovery time before write min 0 ns (oe# high to we# low) tghel read recovery time before write min 0 ns tcs ce# setup time min 0 ns tch ce# hold time min 0 ns twp write pulse width min 35 ns twph wr ite pulse width high min 30 ns write buffer program operation (note 2,3) typ 240 us single word/byte program byte typ 60 us twhwh1 operation (notes 2,5) word typ 60 us accelerated single word/byte byte typ 54 us programming operation (notes 2,5) word typ 54 us twhwh2 sector er ase operation (note 2) typ 0.5 sec tvcs vcc setup time (note 1) min 50 us trb write recovery time from ry/by# min 0 ns tbusy program/erase valid to ry/by# delay min 90 ns tvhh vhh rise and fall time (note 1) min 250 ns tpoll program valid before status polling (note 6) max 4 us notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. 3. for 1-16 words/1-32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. when using the program suspend/resume feature, if the suspend command is issued within tpoll, tpoll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after tpoll, tpoll is not required again prior to reading the status bits upon resuming.
38 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l erase/program operation figure 4. automatic program timing waveforms twc address oe# ce# a0h xxxh pa pd status dout pa pa notes: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc figure 5. accelerated program timing diagram acc tvhh vhh vil or vih vil or vih tvhh
39 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 6. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify word ok ? yes auto program completed data poll from system increment address last address ? no no
40 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 7. write buffer programming algorithm flowchart notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. q7 may change simultaneously with q5. therefore, q7 should be verified. 3. if this flowchart location was reached because q5= "1" then the device failed. if this flowchart location was reached because q1="1", then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if q1=1, write the write-buffer-programming-abort-reset com- mand. if q5=1, write the reset command. 4. see table 3 for command sequences required for write buffer programming. write "write to buffer" command and sector address write number of addresses to program minus 1(wc) and sector address part of "write to buffer" command sequence write program buffer to flash sector address read q7~q0 at last loaded address read q7~q0 with address = last loaded address fail or abort pass write first address/data write next address/data pair write to a different sector address write to buffer aborted. must write "write-to-buffer abort reset" command sequence to return to read mode. wc = wc - 1 wc = 0 ? abort write to buffer operation ? q7 = data ? q5 = 1 ? q1 = 1 ? q7 and q15 = data ? ye s ye s ye s ye s ye s ye s (note 2) (note 1) (note 3) no no no no no no
41 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 8. program suspend/resume flowchart program operation or write-to-buffer sequence in progress write address/data xxxh/b0h write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secured sector read operations are also allowed data cannot be read from erase-or program-suspended sectors write program resume command sequence read data as required write address/data xxxh/30h device reverts to operation prior to program suspend wait 15us done reading ? no ye s
42 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 9. automatic chip/sector erase timing waveform twc address oe# ce# 55h 2aah sa 30h in progress complete va va notes: 1.sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah 555h for chip erase tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph 10 for chip erase tvcs we# data ry/by# vcc
43 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 10. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes write data 10h address 555h write data 55h address 2aah data = ffh ? yes auto erase completed data poll from system no
44 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 11. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah auto sector erase completed data poll from system yes no data=ffh? last sector to erase ? no yes
45 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 12. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
46 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l ac characteristics alternate ce# controlled erase and program operations parameter speed options std. description 90 unit twc write cycle time (note 1) min 90 ns tas address setup time min 0 ns tah address hold time min 45 ns tds data setup time min 35 ns tdh data hold time min 0 ns tghel read recovery time before write min 0 ns (oe# high to we# low) tws we# setup time min 0 ns twh we# hold time min 0 ns tcp ce# pulse width min 35 ns tcph ce# pulse width high min 25 ns write buffer program operation (note 2,3) typ 240 us single word/byte program byte typ 60 us twhwh1 operation (notes 2,5) word typ 60 us accelerated single word/byte byte typ 54 us programming operation (notes 2,5) word typ 54 us twhwh2 sector er ase operation (note 2) typ 0.5 sec trh reset high time before write (note 1) min 50 ns tpoll program v alid before status polling (note 6) max 4 us notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. 3. for 1-16 words/1-32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. when using the program suspend/resume feature, if the suspend command is issued within tpoll, tpoll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after tpoll, tpoll is not required again prior to reading the status bits upon resuming.
47 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 13. ce# controlled program timing waveform twc twh tghel twhwh1 or 2 tcp address we# oe# ce# data q7 pa data# polling dout reset# ry/by# notes: 1.pa=program address, pd=program data, dout=data out, q7=complement of data written to device. 2.figure indicates the last two bus cycles of the command sequence. tah tas pa for program sa for sector erase 555 for chip erase trh tdh tds tws a0 for program 55 for erase tcph tbusy pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase
48 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l sector group protect/chip unprotect figure 14. sector group protect / chip unprotect waveform (reset# control) note: for sector group protect a6=0, a1=1, a0=0. for chip unprotect a6=1, a1=1, a0=0 sector group protect:150us chip unprotect:15ms 1us vid vih data sa, a6 a1, a0 ce# we# oe# valid* valid* status valid* sector group protect or chip unprotect 40h 60h 60h verify reset#
49 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 15. in-system sector group protect/chip unprotect algorithms with reset#=vid start plscnt=1 reset#=vid wait 1us set up sector address sector protect: write 60h to sector address with a6=0, a1=1, a0=0 wait 150us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 reset plscnt=1 remove vid from reset# write reset command sector protect algorithm chip unprotect algorithm sector protect complete remove vid from reset# write reset command sector unprotect complete device failed temporary sector unprotect mode increment plscnt increment plscnt first write cycle=60h? set up first sector address protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect: write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=01h? plscnt=25? device failed start plscnt=1 reset#=vid wait 1us first write cycle=60h? all sectors protected? data=00h? plscnt=1000? last sector verified? ye s ye s ye s no no no ye s ye s ye s ye s ye s ye s no no no no no no protect another sector? reset plscnt=1 temporary sector unprotect mode
50 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 16. sector group protect timing waveform (a9, oe# control) parameter description test setup all speed options unit tvlht vo ltage transition time min. 4 us twpp1 write pulse width for sector group protect min. 100 ns toesp oe# setup time to we# active min. 4 us ac characteristics toe data oe# we# 12v 3v 12v 3v ce# a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h f0h a21-a16 sector address
51 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 17. sector group protection algorithm (a9, oe# control) start set up sector addr plscnt=1 sector protection complete data=01h? ye s . oe#=vid, a9=vid, ce#=vil a6=vil activate we# pulse time out 150us set we#=vih, ce#=oe#=vil a9 should remain vid read from sector addr=sa, a1=1 protect another sector? remove vid from a9 write reset command device failed plscnt=32? ye s no no
52 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 18. chip unprotect timing waveform (a9, oe# control) toe data oe# we# 12v 3v 12v 3v ce# a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 f0h
53 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 19. chip unprotect flowchart (a9, oe# control) start protect all sectors plscnt=1 chip unprotect complete data=00h? ye s set oe#=a9=vid ce#=vil, a6=1 activate we# pulse time out 15ms set oe#=ce#=vil a9=vid, a1=1 set up first sector addr all sectors have been verified? remove vid from a9 write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no increment sector addr * it is recommended before unprotect whole chip, all sectors should be protected in advance.
54 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 20. temporary sector group unprotect waveforms ac characteristics parameter description test all speed options unit setup tvidr vid rise and fall time (see note) min 500 ns trsp reset# setup time for temporary sector unprotect min 4 us trrb reset# hold time from ry/by# high for temporary min 4 us sector group unprotect reset# ce# we# ry/by# tvidr 12v 0 or 3v vil or vih trsp tvidr program or erase command sequence trrb
55 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 21. temporary sector group unprotect flowchart start reset# = vid (note 1) perform erase or program operation reset# = vih temporary sector unprotect completed(note 2) operation completed 2. all previously protected sectors are protected again. note : 1. all protected sectors are temporary unprotected. vid=11.5v~12.5v
56 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 22. secured silicon sector protected algorithms flowchart start enter secured silicon sector data = 01h ? no ye s wait 1us first wait cycle data=60h second wait cycle data=60h a6=0, a1=1, a0=0 wait 300us write reset command device failed secured sector protect complete
57 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 23. silicon id read timing waveform tacc tce tacc toe toh toh tdf data out manufacturer id device id cycle 1 device id cycle 2 device id cycle 3 vid vih vil add a9 add ce# a1 oe# we# add a0 data out data out data out data q0-q15 vcc 3v vih vil vih vil vih vil a2 vih vil vih vil vih vil vih vil vih vil tacc tacc toh toh
58 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l write operation status figure 24. data# polling timing waveforms (during automatic algorithms) notes: va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle . tdf tce tch toe toeh tacc trc toh address ce# oe# we# q7 q0-q6 ry/by# tbusy status data status data status data complement true valid data va va va high z high z valid data tr u e
59 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 25. data# polling algorithm notes: 1.va=valid address for programming. 2.q7 should be rechecked even q5="1" because q7 may change simultaneously with q5. read q7~q0 add.=va(1) read q7~q0 add.=va start q7 = data ? q5 = 1 ? q7 = data ? fail pass no no (2) no ye s ye s ye s
60 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 26. toggle bit timing waveforms (during automatic algorithms) notes: va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tdf tce tch toe toeh tacc trc toh address ce# oe# we# q6/q2 ry/by# tdh valid status valid status (first read) valid status (second read) (stops toggling) valid data va va va va valid data
61 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no (note 1) read q7~q0 twice (note 1,2) toggle bit q6= toggle? program/erase operation not complete, write reset command yes program/erase operation complete figure 27. toggle bit algorithm note: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1".
62 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l figure 28. q6 versus q2 notes: the system can use oe# or ce# to toggle q2/q6, q2 toggles only when read at an address within an erase-suspended we# enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase suspend read erase erase resume erase complete erase q6 q2
63 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics erase and programming performance (1) notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0v vcc. programming specifications assume checkboard data pattern. 2. maximum values are measured at vcc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. for 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see tables 3 for further information on command definitions. 8. the device has a minimum erase and program cycle endurance of 100,000 cycles. parameter min unit minimum pattern data retention time 20 years data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 2 sec excludes 00h programming chip erase time 64 128 sec prior to erasure note 6 total write buffer program time (note 4) 240 us excludes total accelerated effective write buffer 200 us system level program time (note 4) overhead chip program time 63 sec note 7
64 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l parameter symbol parameter description test set typ max unit cin input capacitance vin=0 tsop 6 7.5 pf csp 4.2 5.0 pf cout output capacitance vout=0 tsop 8.5 12 pf csp 5.4 6.5 pf cin2 control pin capacitance vin=0 tsop 7.5 9 pf csp 3.9 4.7 pf tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz
65 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l ordering information part no. access time ball pitch/ package remark (ns) ball size mx29lv640mhtc-90 90 56 pin tsop (normal type) mx29lv640mltc-90 90 56 pin tsop (normal type) mx29lv640mhti-90 90 56 pin tsop (normal type) mx29lv640mlti-90 90 56 pin tsop (normal type) mx29lv641mhtc-90 90 48 pin tsop (normal type) mx29lv641mltc-90 90 48 pin tsop (normal type) mx29lv641mhti-90 90 48 pin tsop (normal type) mx29lv641mlti-90 90 48 pin tsop (normal type)
66 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l part name description mx 29 lv 90 m t t c g option: g: lead-free package r: restricted vcc (3.0v~3.6v) q: restricted vcc (3.0v~3.6v) with lead-free package blank: normal speed: 70: 70ns 90: 90ns 10:100ns temperature range: c: commercial (0?c to 70?c) i: industrial (-40?c to 85?c) package: m: sop t: tsop x: fbga (csp) boot block type: t: top boot b: bottom boot h: uniform with highest sector h/w protect l: uniform with lowest sector h/w protect u: uniform sector revision: m: nbit technology density & mode: 033/320/321: 32mb, page mode flash device 065/640/641: 64mb, page mode flash device 128/129: 128mb, page mode flash device lv/gl: 3v standard la: 3v security type: device: 29:flash xb - 0.3mm ball xe - 0.4mm ball xc - 1.0mm ball 640
67 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l package information
68 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l
69 p/n:pm1093 rev. 1.1, aug. 11, 2005 mx29lv64xm h/l revision history revision no. description page date 1.0 1. removed "preliminary" p1 mar/22/2005 1.1 1. added note 7 for ilit parameter in dc characteristics table p32 aug/11/2005 2. added comments into performance table p63 3. added part name description p66
mx29lv64xm h/l m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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